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Integrated Circuit Systems, Inc.
ICS8304
LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER
FEATURES
* 4 LVCMOS / LVTTL outputs * LVCMOS / LVTTL clock input * Maximum output frequency: 200MHz * Output skew: 45ps (maximum at 3.3V supply) * Part-to-part skew: 500ps (maximum) * Small 8 lead SOIC package saves board space * 3.3V input, outputs may be either 3.3V or 2.5V supply modes * Lead-Free package available * 0C to 70C ambient operating temperature
GENERAL DESCRIPTION
The ICS8304 is a low skew, 1-to-4 Fanout Buffer and a member of the HiPerClockS TM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8304 is characterized at full 3.3V for input VDD, and mixed 3.3V and 2.5V for output operating supply modes (VDDO). Guaranteed output and par t-to-par t skew character istics make the ICS8304 ideal for those clock distribution applications demanding well defined performance and repeatability.
ICS
BLOCK DIAGRAM
Q0
PIN ASSIGNMENT
VDDO VDD CLK GND 1 2 3 4 8 7 6 5 Q3 Q2 Q1 Q0
Q1 CLK Q2
ICS8304
8-Lead SOIC, 150mil 3.9mm x 4.9mm, x 1.63mm package body M Package Top View
Q3
8304AM
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1
REV. F SEPTEMBER 13, 2004
Integrated Circuit Systems, Inc.
ICS8304
LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER
Type Power Power Input Power Output Output Output Output Pulldown Description Output supply pin. Core supply pin. LVCMOS / LVTTL clock input. Power supply ground. Single clock output. LVCMOS / LVTTL interface levels. Single clock output. LVCMOS / LVTTL interface levels. Single clock output. LVCMOS / LVTTL interface levels. Single clock output. LVCMOS / LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 8 Name VDDO VDD CLK GND Q0 Q1 Q2 Q3
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pulldown Resistor Output Impedance Test Conditions Minimum Typical 4 VDD, VDDO = 3.465V 51 5 7 12 15 Maximum Units pF pF K
8304AM
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REV. F SEPTEMBER 13, 2004
Integrated Circuit Systems, Inc.
ICS8304
LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 112.7C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 15 8 Units V V mA mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL VOH Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V Refer to NOTE 1 IOH = -16mA IOH = -100uA Refer to NOTE 1 VOL Output Low Voltage IOL = 16mA IOL = 100uA -5 2. 6 2.9 3 0.5 0.25 0.15 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 1.3 150 Units V V A A V V V V V V
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Section, "3.3V Output Load Test Circuit".
TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 15 8 Units V V mA mA
8304AM
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3
REV. F SEPTEMBER 13, 2004
Integrated Circuit Systems, Inc.
ICS8304
LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER
Test Conditions Minimum 2 -0.3 VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -5 2.1 0.5 Typical Maximum VDD + 0.3 1.3 150 Units V V A A V V
TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VIH VIL IIH IIL VOH Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Section, "3.3V/2.5V Output Load Test Circuit".
TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter fMAX tpLH Maximum Output Frequency Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time 30% to 70% 30% to 70% 250 250 166MHz 166MHz < f 189.5MHz = 133MHz 2.0 2.0 Test Conditions Minimum Typical Maximum 200 3.3 3.4 45 500 500 500 60 Units MHz ns ns ps ps ps ps %
tsk(o) tsk(pp)
tR tF
odc Output Duty Cycle f 189.5MHz 40 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter fMAX tpLH Maximum Output Frequency Propagation Delay, Low-to-High; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time 30% to 70% 30% to 70% 250 250 166MHz 166MHz < f 189.5MHz = 133MHz 2.3 2.15 Test Conditions Minimum Typical Maximum 189.5 3.7 3.55 60 500 500 500 60 Units MHz ns ns ps ps ps ps %
tsk(o) tsk(pp)
tR tF
odc Output Duty Cycle f 189.5MHz 40 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8304AM
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4
REV. F SEPTEMBER 13, 2004
Integrated Circuit Systems, Inc.
ICS8304
LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 2.05V5% 1.25V5%
VDD, VDDO
SCOPE
Qx
VDD VDDO
Qx
SCOPE
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
V
DD
PART 1 Qx
V
DD
Qx
2
2
V
PART 2 Qy
DD
V
DD
Qy
2 tsk(o)
2 tsk(pp)
OUTPUT SKEW
70% 30%
tR tF 70%
PART-TO-PART SKEW
V Q0:Q3
DDO
2 Pulse Width t
PERIOD
Clock Outputs
30%
odc =
t PW t PERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
CLK
VDD 2
Q0:Q3
VDDO 2 t
PD
PROPAGATION DELAY
8304AM
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5
REV. F SEPTEMBER 13, 2004
Integrated Circuit Systems, Inc.
ICS8304
LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 5.
JAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0 200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards
153.3C/W 112.7C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8304 is: 416
8304AM
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6
REV. F SEPTEMBER 13, 2004
Integrated Circuit Systems, Inc.
ICS8304
LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER
FOR
PACKAGE OUTLINE - SUFFIX M
8 LEAD SOIC
TABLE 6. PACKAGE DIMENSIONS - SUFFIX M
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
8304AM
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7
REV. F SEPTEMBER 13, 2004
Integrated Circuit Systems, Inc.
ICS8304
LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER
Marking 8304AM 8304AM Package 8 lead SOIC 8 lead SOIC on Tape and Reel 8 lead SOIC, "Lead Free/Annealed" 8 lead SOIC, "Lead Free/Annealed" on Tape and Reel 8 lead SOIC, "Lead Free" 8 lead SOIC, "Lead Free" on Tape and Reel Count 96 per tube 2500 96 per tube 2500 96 per tube 2500 Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 7. ORDERING INFORMATION
Part/Order Number ICS8304AM ICS8304AMT ICS8304AMLN ICS8304AMLNT ICS8304AMLF ICS8304AMLFT
8304AMLN 8304AMLN 8304AMLF 8304AMLF
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8304AM
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8
REV. F SEPTEMBER 13, 2004
Integrated Circuit Systems, Inc.
ICS8304
LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change Revised tpLH (Propagation Delay) row from 2.3 Min. to 2 Min. Deleted tpHL row. Revised tsk(o) (Output Skew) row from 35 Max. to 80 Max. Revised tsk(pp) (Par t-to-Par t Skew) row from 200 Max. to 500 Max. General note changed from "...measured at 166MHz..." to " ...measured at 150MHz..." Date 12/4/01
Rev B
Table T4A
Page 3
* * * * *
T4B
4
C
T4A
3
* Revised tpLH (Propagation Delay) row from 2.6 Min. to 2.3 Min. * Deleted tpHL row. * Revised tsk(o) (Output Skew) row from 35 Max. to 85 Max. * Revised tsk(pp) (Par t-to-Par t Skew) row from 200 Max. to 500 Max. * General note changed from "...measured at 166MHz..." to " ...measured at 150MHz..." * In AC table, revised tsk(o) row from 80ps Max. to 45ps Max. Added f = 133MHz in Test Conditions column. * In odc row, deleted test conditions. * In notes, changed 150MHz to fMAX. * In AC table, revised tsk(o) row from 80ps Max. to 60ps Max. Added f = 133MHz in Test Conditions column. * In odc row, deleted test conditions * In notes, changed 150MHz to fMAX. In the Ordering Information table, Marking column, revised marking to read 8304AM from ICS8304AM. LVCMOS/LVTTL DC Characteristics Table, added IOH and IOL Test Conditions to VOH and VOL rows. * Pin Assignment - adjusted dimensions. * Pin Descriptions - changed VDD description to Core supply pin. * Pin Characteristics - changed CIN max 4pF to typical 4pF. Deleted RPULLUP row. Added 5 min. and 12 max. to ROUT. * Power Supply tables - changed VDD parameter from Power to Core. * Ordering Information table - added "Lead Free/Annealed" marking. Updated format throughout the data sheet. Featues section, changed Maximum output frequency bullet from 166MHz to 200MHz. 3.3V AC Table - changed 166MHz max. to 200MHz max. Added another line for Propagation Delay. Changed test conditions in Output Duty Cycle from 166MHz to 189.5MHz. 3.3V AC Table - changed 166MHz max. to 189.5MHz max. Added another line for Propagation Delay. Changed test conditions in Output Duty Cycle from 166MHz to 189.5MH * Ordering Information table - added "Lead Free" marking.
12/11/01
T4B
4
C D
T7 T3B
10 3 1 2 2
3/11/02 4/4/02
T1 T2 E T3A & T3C T7
4/13/04
3&4 8 1
T4A F T4B
4
6/1/04
4
F
T7
8
9/13/04
8304AM
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REV. F SEPTEMBER 13, 2004

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